List of Selected Papers
VISA
We are excited to showcase groundbreaking research and innovation from the brightest minds in the fields of Integrated Circuits and Systems. This year’s conference has attracted contributions from leading researchers, engineers, and innovators from around the world, focusing on cutting-edge advancements in VLSI, semiconductor technologies, and related fields. Below, you will find the complete list of accepted papers, covering a diverse range of topics that push the boundaries of technology and design. Each paper represents a significant contribution to the global scientific community, presenting novel ideas, methodologies, and solutions that address the challenges of today and shape the technologies of tomorrow. Whether you are a researcher, an industry professional, or simply passionate about electronics and semiconductor advancements, we invite you to explore these papers and engage with the authors at the conference.
Each of these papers is a testament to the incredible work being done in our community and offers valuable insights for academics, industry professionals, and students alike.
Selected Papers List
| Paper ID | Paper Title | Author Names |
|---|---|---|
| PID_1 | An Offset-Cancellation Technique Using Charge-Trap Transistors and Asynchronous Programming Scheme | Du, Li |
| PID_2 | Ultra-Low-Power High PSRR Sub-1V Voltage Reference Circuit in 22nm FDSOI CMOS | Dossanov, Adilet |
| PID_3 | Analysis and Design of a Self-bias Cross-coupled CMOS Rectifier to Enhance Input Power Range | Terence, Teo Boon Chiat; Lim, Wu Cong; Rabeek, S. Mohamed; Raja, M. Kumarasamy; Navaneethan, Venkadasamy; Lim, Xian Yang; Siek, Liter |
| PID_4 | 0.4-V Supply, 12-nW Reverse Bandgap Voltage Reference with Single BJT and Indirect Curvature Compensation | Lee, Chon-Fai; U, Chi-Wa; Martins, Rui; Lam, Chi-Seng |
| PID_5 | A Dual-Channel Pseudo-Differential Analog Front-end Circuit for Fluorescence Optical Fiber Temperature Sensor | Xiong, Bingjun; Liu, Jingjing; Yang, Jian; Wang, Yang |
| PID_6 | A High-Voltage Differential SPDT T/R Switch for Ultrasound Systems | Zhang, Yaohua; Jiang, Dai; Demosthenous, Andreas |
| PID_7 | Up to 45% Faster Supply Boosted Voltage Sense Amplifier (SBVSA) for High-Speed SRAMs | Sharma, Rachit |
| PID_8 | A 10.23-bit ENOB 1 kS/s Differential VCO-based ADC with Resistive Input Stage in Low-Temperature Poly-Silicon TFT Technology | Zhao, Jian |
| PID_9 | A 4.3 GS/s Time-Interleaved ∆Σ DAC with Temperature-Insensitive Bias and Harmonic Cancellation for Qubit Control | NAM, JAEWON |
| PID_10 | Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC | Kye, Chan-Ho; Byeon, Yu-Jin; Choo, Kyojin; Choo, Min-Seong |
| PID_11 | A 0.6-V 4-MS/s Asynchronous SAR ADC With 2-bit Conversion/cycle Time-Domain Comparator | Lee, Won-Young |
| PID_12 | Artificial Neural Network Based Calibration for a 12b 250MS/s Pipelined-SAR ADC with Ring Amplifier in 40-nm CMOS | Liu, Bin; Li, Nannan; Chen, Xuhui; Dai, Zhichao; Ge, Yufeng; Jiang, Zheng; Qi, Huanhuan; Zhang, Jie; Wang, Jinfu; Wang, Xiaofei; Chen, Zhenhai; Xue, Yan; Zhang, Hong |
| PID_13 | A 512-nW 0.003-mm2 Forward-Forward Black Box Trainer for an Analog Voice Activity Detector in 28-nm CMOS | Yu, Wei Han |
| PID_14 | An 11T1C Bit-Level-Sparsity-Aware Computing-in-Memory Macro with Adaptive Conversion Time and Computation Voltage | Lin, Ye; Li, Yuandong; Zhang, Heng; Ma, He; Lv, Jingjing; Jiang, Anying; Du, Yuan; Du, Li |
| PID_15 | CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro with Signed-Channel Training and Weight Updating for Nonuniform Quantization | Fu, Yuzhao; Li, Jixuan; Yu, Wei-Han; Un, Ka-Fai; Chan, Chi-hang; Zhu, Yan; Martins, Rui; Mak, Pui In |
| PID_16 | A 22-nA Quiescent Current, 50-mA Output-Capacitor-Less Low-Dropout Regulator With Multiple-Feedback Loop for IoT Devices | Chatterjee, Shouri |
| PID_17 | A Ripple-Based Real-Time Built-In-Resistance Compensation for Switching Battery Charger Achieving Fast Charging | Cho, Kunhee |
| PID_18 | A 2 µA Iq Passive-Ramp-Adaptive-Extended-TON Controlled Buck Converter Leveraging Clamped Adaptive Biased Error Amplifier to Achieve DVS/Load Transient One-Cycle Recovery Time | Tsai, Chieh-Ju; Chen, Hsiao-Hsuan; Chen, Ching-Jan |
| PID_19 | A 2.5-A 3-ns-Response-Time Calibration-Free Hybrid LDO Using Scalable Self-Clocked Stochastic Flash-ADC for In-Loop Quantization | Lyu, Tianrui; Wang, Zixin; Guo, Jianping |
| PID_20 | A High-PSRR NMOS LDO Regulator with Intrinsic Gain-Tracking Ripple Cancellation Technique | Kim, Jung Sik; Ha, Seunggyun; Jeong, Hongyup; Roh, Jeongjin |
| PID_21 | An All NMOS KY-Boost Converter with Double Injection Control for Fast Line and Load Transient Response | Hung, Yu-Ting; Tsai, Chieh-Ju; Chen, Ching-Jan; Hsu, Chan-Hsuan; Hsieh, Chun-Yu |
| PID_22 | On-chip Configurable RF Energy Harvester for Biomedical Implantable Devices | S, Nagaveni; Hunasigidad, Praveen; Pathak, Deepali; Dutta, Ashudeb |
| PID_23 | A DVS-Enabled Distributed Digital LDO Providing Rapid Uniform Power Grid and Ripple Reduction Achieving 20.1-ps FOM in 28nm CMOS | Han, Yuli; Kim, Jaemin; Koo, Gunmo; Kim, Jaejin; Kim, Jusung; Kim, Joo-Young; Cho, Kunhee |
| PID_24 | Two-phase Hybrid Buck-Boost Converter with Coupled-Inductors under ZVS Operation for USB PD Bidirectional Conversion | Chiu, Yi-Ching; Tseng, Nan-Hsiung; Liao, Chih-Cherng; Guan, Hao-Wen; Chang, Po-Shiun; Chen, Ke-Horng; Zheng, Kuo-Lin; Lin, Ying-Hsi; Lin, Shian-Ru; Tsai, Tsung-Yen |
| PID_25 | A Phase Interpolated Dual-Phase Adaptive On-Time Controlled Buck Converter | Tsai, Chieh-Ju; Chen, Hsiao-Hsuan; Chen, Ching-Jan |
| PID_26 | A Wireless-Powered Battery-Less Electrical Stimulator with Delay-Shift Keying (DSK) Based Downlink Data Communication | Yao, Daohan; Hung, Chia-Ching; Lo, Wen-Po; Chen, Po-Hung |
| PID_27 | Enhancing Continuous Beam Angle Resolution for Next Generation Wireless Systems: A Multi-Stage Phase-Shifting Polyphase Filters Approach | Slater, Adam; Abbasi, Hesam; Poolakkal, Sreeni; Behesti, Foad; Gupta, Subhanshu |
| PID_28 | A 102-Gb/s/lane 1.4-Vppd Linear Range PAM-8 Receiver Frontend with Multi-Path Continuous-Time Linear Equalization in 28-nm CMOS | Han, Jaeduk |
| PID_29 | A 3×12-Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter with Crosstalk Cancellation Technique in 28-nm CMOS | Park, Kwanseo |
| PID_30 | A 0.09-pJ/b/dB 28-Gb/s Digital CDR with ISI-Resistant Phase Detector | Park, Kwanseo |
| PID_31 | High-Precision Built-In Phase Noise Measurement Circuit with a Hybrid ∆Σ Time-to-Digital Converter for SoC Clocking Applications | Roh, Jeongjin |
| PID_32 | A 5.4-7.4GHz Ultra-Low Jitter Injection-Locked Frequency Tripler with 3rd Harmonic Current Boosting Input Buffer | Sadhukhan, Sonam |
| PID_33 | A 32-Gb/s Single-Ended PAM-4 Transceiver with Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces | Kim, Hyuntae; Jo, Yunseong; Lee, Sanghun; Lee, Eunsang; Choi, Young; Park, Jaewoo; Kwak, Myoungbo; Choi, Junghwan; Choi, Youngdon; Han, Jaeduk |
| PID_34 | A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-based Wireline Transceivers | Kim, Donggeon; Choi, Yujin; Lee, Jaewon; Jang, Seoyoung; Song, Sungyu; Braendli, Matthias; Morf, Thomas; Kossel, Marcel; Francese, Pier; Kim, Gain |
| PID_35 | Mobile-X: Dedicated FPGA Implementation of the MobileNet Accelerator Optimizing Depthwise Separable Convolution | Kim, Hyun |
| PID_36 | A Configurable ML-KEM/Kyber Key-Encapsulation Hardware Accelerator Architecture | Lee, Hanho |
| PID_37 | RAW Images-based Motion-assisted Object Detection Accelerator Using Deformable Parts Models Features on 1080p Videos | Zhang, Ling; Li, Haoyan; Zhang, Xiangyu; Lou, Xin |
| PID_38 | A Real-Time and High Precision Hardware Implementation of RANSAC Algorithm for Visual SLAM Achieving Mismatched Feature Point Pair Elimination | He, Wenzheng; Lu, Zikuo; Liu, Xin; Xu, Ziwei; Zhang, Jinshuo; Yang, Chen; Geng, Li |
| PID_39 | Accelerated Image Processing through IMPLY-Based NoCarry Approximated Adders | Seiler, Fabian; TaheriNejad, Nima |
| PID_40 | High Logic Density Cyclic Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit for JESD204C Controller | Chen, Hongli; Yin, Peng; Xia, Yingjun; Zhang, Jinlong; Liu, Mingguo; Gu, Cheng; Hou, Weizhou; Bermak, Amine; Tang, Fang |
| PID_41 | An Efficient FPGA-based Dilated and Transposed Convolutional Neural Network Accelerator | Wu, Tsung-Hsi; Shu, Chang; Liu, Tsung-Te |
| PID_42 | An FPGA-Based Transformer Accelerator with Parallel Unstructured Sparsity Handling for Question-Answering Applications | Un, Ka-Fai |
| PID_43 | An N/PBTI-Isolated BTI Monitor With a Configurable Switching Network and Calibration for Process Variation in Memory Periphery | Kim, Suhwan |
| PID_44 | An M-metric Readout Circuit for MLC Phase Change Memory with a Comparator-Based Push-Pull Bit-Line Driver | Seo, Min-Jae |
| PID_45 | A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured By Genetic Algorithm | Wang, Chua-Chin; L S S, Pavan Kumar Chodisetti; Ke, Jhih-Ying; Lo, Cheng-Yao; Lee, Tzung-Je; Tolentino, Lean Karlo Santos |
| PID_46 | Area-Delay-Energy-Efficient Approximate Dividers based on Piecewise Linear Fitting of Surface | Wu, Chaoyuan; Shi, Weiwei; Yuan, Yida; Zou, Zhuoliang; Mo, Zhihong; He, Jiangwei |
| PID_47 | De-correlation and De-bias Post-processing Circuits for True Random Number Generator | Zhang, Ruilin; Zhang, Haochen; Wang, xingyu; Ziyang, Ye; Liu, Kunyang; NISHIZAWA, SHINICHI; Niitsu, Kiichi; Shinohara, Hirofumi |
| PID_48 | BiNPU: A 33.0 MOP/s/LUT Binary Neural Network Inference Processor Showing 88.26% CIFAR10 Accuracy with 1.9 Mbit On-Chip Parameters in a 28 nm FPGA | Kim, Tae-Hwan |