Conference Agenda
Agenda
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Day 0
17 Oct 2024
Thursday
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Day 1
18 Oct 2024
Friday
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Day 2
19 Oct 2024
Saturday
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Day 3
20 Oct 2024
Sunday
Optional Day Trip
Explore the iconic Taj Mahal, Agra. This excursion is available at an additional cost. For more details and to reserve your spot, please contact isicas2024@gmail.com.
| IEEE International Symposium on Integrated Circuits and Systems (ISICAS 2024) | ||||
| Start | End | Duration | Session 1 | Session 2 |
| Day 1 | 18 October 2024 | Friday | ||||
| 8:30 | 9:00 | 0:30 | Welcome/Registration | |
| 9:00 | 9:30 | 0:30 | Inauguration Ceremony | |
| 9:30 | 10:00 | 0:30 | Visionary Keynote Talk | |
| 10:00 | 11:00 | 1:00 | Panel Discussion | |
| 11:00 | 11:30 | 0:30 | Tea / Coffee Break | |
| 11:30 | 13:00 | 1:30 | Technical Papers Session: 1A |
Technical Papers Session: 1B |
| PID_22 : On-chip
Configurable RF Energy Harvester for Biomedical Implantable Devices (S, Nagaveni; Hunasigidad, Praveen; Pathak, Deepali; Dutta, Ashudeb) |
PID_43 : An N/PBTI-Isolated BTI Monitor
With a Configurable Switching Network and Calibration for Process Variation
in Memory Periphery (Kim, Suhwan) |
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| PID_20 : A
High-PSRR NMOS LDO Regulator with Intrinsic Gain-Tracking Ripple Cancellation
Technique (Kim, Jung Sik; Ha, Seunggyun; Jeong, Hongyup; Roh, Jeongjin) |
PID_45 : A 6-Gbps 16-nm FinFET CMOS I/O
Buffer With Variation Insensitivity Ensured By Genetic Algorithm (Wang, Chua-Chin; L S S, Pavan Kumar Chodisetti; Ke, Jhih-Ying; Lo, Cheng-Yao; Lee, Tzung-Je; Tolentino, Lean Karlo Santos) |
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| PID_23 : A
DVS-Enabled Distributed Digital LDO Providing Rapid Uniform Power Grid and
Ripple Reduction Achieving 20.1-ps FOM in 28nm CMOS (Han, Yuli; Kim, Jaemin; Koo, Gunmo; Kim, Jaejin; Kim, Jusung; Kim, Joo-Young; Cho, Kunhee) |
PID_44 : An M-metric Readout Circuit for
MLC Phase Change Memory with a Comparator-Based Push-Pull Bit-Line Driver (Seo, Min-Jae) |
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| PID_27 : Enhancing
Continuous Beam Angle Resolution for Next Generation Wireless Systems: A
Multi-Stage Phase-Shifting Polyphase Filters Approach (Slater, Adam; Abbasi, Hesam; Poolakkal, Sreeni; Behesti, Foad; Gupta, Subhanshu) |
PID_48 : BiNPU: A 33.0 MOP/s/LUT Binary
Neural Network Inference Processor Showing 88.26% CIFAR10 Accuracy with 1.9
Mbit On-Chip Parameters in a 28 nm FPGA (Kim, Tae-Hwan) |
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| 13:00 | 14:00 | 1:00 | Lunch Break | |
| 14:00 | 15:30 | 1:30 | Technical Papers Session: 2A |
Technical Papers Session: 2B |
| PID_25 : A Phase
Interpolated Dual-Phase Adaptive On-Time Controlled Buck Converter (Tsai, Chieh-Ju; Chen, Hsiao-Hsuan; Chen, Ching-Jan) |
PID_1 : An Offset-Cancellation Technique
Using Charge-Trap Transistors and Asynchronous Programming Scheme (Du, Li) |
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| PID_26 : A
Wireless-Powered Battery-Less Electrical Stimulator with Delay-Shift Keying
(DSK) Based Downlink Data Communication (Yao, Daohan; Hung, Chia-Ching; Lo, Wen-Po; Chen, Po-Hung) |
PID_4 : 0.4-V Supply, 12-nW Reverse
Bandgap Voltage Reference with Single BJT and Indirect Curvature Compensation (Lee, Chon-Fai; U, Chi-Wa; Martins, Rui; Lam, Chi-Seng) |
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| PID_28 : A
102-Gb/s/lane 1.4-Vppd Linear Range PAM-8 Receiver Frontend with Multi-Path
Continuous-Time Linear Equalization in 28-nm CMOS (Han, Jaeduk) |
PID_2 : Ultra-Low-Power High PSRR Sub-1V
Voltage Reference Circuit in 22nm FDSOI CMOS (Dossanov, Adilet) |
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| PID_29 : A 3×12-Gb/s
1.26-pJ/b Single-Ended PAM-3 Transmitter with Crosstalk Cancellation
Technique in 28-nm CMOS (Park, Kwanseo) |
PID_5 : A Dual-Channel
Pseudo-Differential Analog Front-end Circuit for Fluorescence Optical Fiber
Temperature Sensor (Xiong, Bingjun; Liu, Jingjing; Yang, Jian; Wang, Yang) |
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| 15:30 | 16:00 | 0:30 | Tea / Coffee Break | |
| 16:00 | 17:30 | 1:30 | Technical Papers Session: 3A |
Technical Papers Session: 3B |
| PID_30 : A 0.09-pJ/b/dB
28-Gb/s Digital CDR with ISI-Resistant Phase Detector (Park, Kwanseo) |
PID_6 : A High-Voltage Differential SPDT
T/R Switch for Ultrasound Systems (Zhang, Yaohua; Jiang, Dai; Demosthenous, Andreas) |
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| PID_31 : High-Precision
Built-In Phase Noise Measurement Circuit with a Hybrid ∆Σ
Time-to-Digital Converter for SoC Clocking Applications (Roh, Jeongjin) |
PID_8 : A 10.23-bit ENOB 1 kS/s
Differential VCO-based ADC with Resistive Input Stage in Low-Temperature
Poly-Silicon TFT Technology (Zhao, Jian) |
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| PID_32 : A 5.4-7.4GHz
Ultra-Low Jitter Injection-Locked Frequency Tripler with 3rd Harmonic Current
Boosting Input Buffer (Sadhukhan, Sonam) |
PID_12 : Artificial Neural Network Based
Calibration for a 12b 250MS/s Pipelined-SAR ADC with Ring Amplifier in 40-nm
CMOS (Liu, Bin; Li, Nannan; Chen, Xuhui; Dai, Zhichao; Ge, Yufeng; Jiang, Zheng; Qi, Huanhuan; Zhang, Jie; Wang, Jinfu; Wang, Xiaofei; Chen, Zhenhai; Xue, Yan; Zhang, Hong) |
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| PID_33 : A 32-Gb/s
Single-Ended PAM-4 Transceiver with Asymmetric Termination and Equalization
Techniques for Next-Generation Memory Interfaces (Kim, Hyuntae; Jo, Yunseong; Lee, Sanghun; Lee, Eunsang; Choi, Young; Park, Jaewoo; Kwak, Myoungbo; Choi, Junghwan; Choi, Youngdon; Han, Jaeduk) |
PID_13 : A 512-nW 0.003-mm2
Forward-Forward Black Box Trainer for an Analog Voice Activity Detector in
28-nm CMOS (Yu, Wei Han) |
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| 17:30 | 18:00 | 0:30 | Networking Break | |
| 18:00 | 19:00 | 1:00 | Cultural Evening | |
| 19:00 | 20:30 | 1:30 | Ethnic Evening Dinner with Dance and Music | |
| IEEE International Symposium on Integrated Circuits and Systems (ISICAS 2024) | ||||
| Start | End | Duration | Session 1 | Session 2 |
| Day 2 | 19 October 2024 | Saturday | ||||
| 8:30 | 9:00 | 0:30 | Welcome/Registration | |
| 9:00 | 9:30 | 0:30 | Visionary Keynote Talk | |
| 9:30 | 10:00 | 0:30 | Visionary Keynote Talk | |
| 10:00 | 11:00 | 1:00 | Panel Discussion | |
| 11:00 | 11:30 | 0:30 | Tea / Coffee Break | |
| 11:30 | 13:00 | 1:30 | Technical Papers Session:4A |
Technical Papers Session: 4B |
| PID_3 : Analysis
and Design of a Self-bias Cross-coupled CMOS Rectifier to Enhance Input Power
Range (Terence, Teo Boon Chiat; Lim, Wu Cong; Rabeek, S. Mohamed; Raja, M. Kumarasamy; Navaneethan, Venkadasamy; Lim, Xian Yang; Siek, Liter) |
PID_34 : A Loop-Break Decision Feedback
Equalizer for DAC/ADC-DSP-based Wireline Transceivers (Kim, Donggeon; Choi, Yujin; Lee, Jaewon; Jang, Seoyoung; Song, Sungyu; Braendli, Matthias; Morf, Thomas; Kossel, Marcel; Francese, Pier; Kim, Gain) |
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| PID_7 : Up to 45%
Faster Supply Boosted Voltage Sense Amplifier (SBVSA) for High-Speed SRAMs (Sharma, Rachit) |
PID_36 : A Configurable ML-KEM/Kyber
Key-Encapsulation Hardware Accelerator Architecture (Lee, Hanho) |
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| PID_9 : A 4.3 GS/s
Time-Interleaved ∆Σ DAC with Temperature-Insensitive Bias and
Harmonic Cancellation for Qubit Control (NAM, JAEWON) |
PID_35 : Mobile-X: Dedicated FPGA
Implementation of the MobileNet Accelerator Optimizing Depthwise Separable
Convolution (Kim, Hyun) |
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| PID_11 : A 0.6-V 4-MS/s
Asynchronous SAR ADC With 2-bit Conversion/cycle Time-Domain Comparator (Lee, Won-Young) |
PID_39 : Accelerated Image Processing
through IMPLY-Based NoCarry Approximated Adders (Seiler, Fabian; TaheriNejad, Nima) |
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| 13:00 | 14:00 | 1:00 | Lunch Break | |
| 14:00 | 15:30 | 1:30 | Technical Papers Session: 5A |
Technical Papers Session: 5B |
| PID_10 : Design
Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted
Charge-Injection DAC-Based SAR ADC (Kye, Chan-Ho; Byeon, Yu-Jin; Choo, Kyojin; Choo, Min-Seong) |
PID_14 : An 11T1C
Bit-Level-Sparsity-Aware Computing-in-Memory Macro with Adaptive Conversion
Time and Computation Voltage (Lin, Ye; Li, Yuandong; Zhang, Heng; Ma, He; Lv, Jingjing; Jiang, Anying; Du, Yuan; Du, Li) |
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| PID_16 : A 22-nA
Quiescent Current, 50-mA Output-Capacitor-Less Low-Dropout Regulator With
Multiple-Feedback Loop for IoT Devices (Chatterjee , Shouri) |
PID_15 : CLUT-CIM: A Capacitance Lookup
Table-Based Analog Compute-in-Memory Macro with Signed-Channel Training and
Weight Updating for Nonuniform Quantization (Fu, Yuzhao; Li, Jixuan; Yu, Wei-Han; Un, Ka-Fai; Chan, Chi-hang; Zhu, Yan; Martins, Rui; Mak, Pui In) |
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| PID_17 : A Ripple-Based Real-Time
Built-In-Resistance Compensation for Switching Battery Charger Achieving Fast
Charging (Cho, Kunhee) |
PID_19 : A 2.5-A 3-ns-Response-Time
Calibration-Free Hybrid LDO Using Scalable Self-Clocked Stochastic Flash-ADC
for In-Loop Quantization (Lyu, Tianrui; Wang, Zixin; Guo, Jianping) |
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| PID_18 : A 2 µA Iq
Passive-Ramp-Adaptive-Extended-TON Controlled Buck Converter Leveraging
Clamped Adaptive Biased Error Amplifier to Achieve DVS/Load Transient
One-Cycle Recovery Time (Tsai, Chieh-Ju; Chen, Hsiao-Hsuan; Chen, Ching-Jan) |
PID_21 : An All NMOS KY-Boost Converter
with Double Injection Control for Fast Line and Load Transient Response (Hung, Yu-Ting; Tsai, Chieh-Ju; Chen, Ching-Jan; Hsu, Chan-Hsuan; Hsieh, Chun-Yu) |
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| 15:30 | 16:00 | 0:30 | Tea / Coffee Break | |
| 16:00 | 17:30 | 1:30 | Technical Papers Session: 6A |
Technical Papers Session: 6B |
| PID_41 : An Efficient FPGA-based Dilated
and Transposed Convolutional Neural Network Accelerator (Wu, Tsung-Hsi; Shu, Chang; Liu, Tsung-Te) |
PID_24 : Two-phase Hybrid Buck-Boost
Converter with Coupled-Inductors under ZVS Operation for USB PD Bidirectional
Conversion (Chiu, Yi-Ching; Tseng, Nan-Hsiung; Liao, Chih-Cherng; Guan, Hao-Wen; Chang, Po-Shiun; Chen, Ke-Horng; Zheng, Kuo-Lin; Lin, Ying-Hsi; Lin, Shian-Ru; Tsai, Tsung-Yen) |
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| PID_42 : An
FPGA-Based Transformer Accelerator with Parallel Unstructured Sparsity
Handling for Question-Answering Applications (Un, Ka-Fai) |
PID_37 : RAW Images-based
Motion-assisted Object Detection Accelerator Using Deformable Parts Models
Features on 1080p Videos (Zhang, Ling; Li, Haoyan; Zhang, Xiangyu; Lou, Xin) |
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| PID_46 :
Area-Delay-Energy-Efficient Approximate Dividers based on Piecewise Linear
Fitting of Surface (Wu, Chaoyuan; Shi, Weiwei; Yuan, Yida; Zou, Zhuoliang; Mo, Zhihong; He, Jiangwei) |
PID_38 : A Real-Time and High Precision
Hardware Implementation of RANSAC Algorithm for Visual SLAM Achieving
Mismatched Feature Point Pair Elimination (He, Wenzheng; Lu, Zikuo; Liu, Xin; Xu, Ziwei; Zhang, Jinshuo; Yang, Chen; Geng, Li) |
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| PID_47 :
De-correlation and De-bias Post-processing Circuits for True Random Number
Generator (Zhang, Ruilin; Zhang, Haochen; Wang, xingyu; Ziyang, Ye; Liu, Kunyang; NISHIZAWA, SHINICHI; Niitsu, Kiichi; Shinohara, Hirofumi) |
PID_40 : High Logic Density Cyclic
Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit
for JESD204C Controller (Chen, Hongli; Yin, Peng; Xia, Yingjun; Zhang, Jinlong; Liu, Mingguo; Gu, Cheng; Hou, Weizhou; Bermak, Amine; Tang, Fang) |
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| 17:30 | 18:00 | 0:30 | Networking Break | |
| 18:00 | 18:30 | 0:30 | Awards Ceremony | |
Satellite Workshop as part of the ISICAS2024 conference.
Or
Optional Day Trip: Discover the vibrant city of Delhi. Experience its rich history and culture with a guided tour. For more details and to reserve your spot, please contact isicas2024@gmail.com.
Or
For sports enthusiasts: The famous Delhi Half Marathon takes place on 20th October 2024. Whether you're a runner or a supporter, it's a great opportunity to experience this vibrant city event. For more details and registration information, visit the official marathon webpage.
Registration Dates for Marathon:
Starts: on Friday, 19th July 2024, 7 AM IST
Ends: on Friday, 20th September 2024, 11:59 PM IST
Please note that the conference team has no role to play regarding registration or any queries related to the marathon. Please refer to the marathon webpage for any assistance.